DRAMs are typically formed of orthogonally disposed word lines and bit lines, with charge storage cells adjacent each intersection addressed via the wordlines and connected to the bit lines. Each charge storage cell stores a charge received from a bit line when it is addressed, that designates the value (0 or 1) of a bit. Bit lines are typically in a well known folded form, formed of two conductors, that interface a data bus via a sense amplifier and column access devices, such as field effect switches that are addressed via a column decoder.
Pertinent circuitry of a typical prior art DRAM is illustrated in FIG. 1. A charge storage cell 1 is formed of a capacitor 2A connected in series with a field effect transistor 2B (FET) between a voltage supply Vcc and a conductor of a folded bitline 3. The gate of the FET is connected to a wordline 4. The bitline is connected to a sense amplifier 5. Each output conductor of the sense amplifier is connected through an FET 6 to a corresponding conductor of a data bus 8. The gates of FETs 6 are connected together to the output of a column decoder, which provides the control signal Yj, Y(j+1) which is a decoded column address signal to those gates.
The conductors of data bus 8 are connected differentially to the input of a read amplifier 9 and to the output of a write amplifier 10. A source of precharge voltage Vcc/2 is applied from leads Vblp via precharge control FETs 12A, 12B and 13A, 13B to corresponding conductors of the data bus 8 and to the folded bitline 3 respectively. The pairs of conductors of data bus 8 and the conductors of bitline 3 can also be connected together for equalization through FETs 14 and 15 respectively. The gates of FETs 12A, 12B and 14 are connected to a source of a gate precharge enable control signal, PRE. Gates of FETs 13A, 13B and 15 are connected together and to a bitline precharge enable control signal. A write enable signal WMA is provided to a control input of the write amplifier, and a read enable signal RMA is provided to a control input of the read amplifier.
A page of a DRAM is defined as the memory locations accessed by a unique row address. After sensing, a page of data is held in the bitline sense amplifiers and can be accessed in small increments addressed by the Y-decoder.
It is sometimes desired to copy data from one page of the DRAM to another. In such cases it was necessary to read the data out of each column address location of the page sequentially and to write the read data into a column address, using a location on another page address cycle for each read and a row address and column address cycle for each row and column write step.
FIG. 2 illustrates a write sequence for a single column address in the aforenoted operation. Bitline precharge voltage is applied to bitlines 3 for an interval 20, and is then disabled, leaving the bitlines floating. A wordline 4 is addressed for a period of time 22. Upon addressing a wordline, data stored in the capacitors of memory cells 2A is passed to the respective folded bitlines, as indicated at 24A, 24B, 24C and 24D. The level is attenuated due to charge sharing between cell capacitance and bitline capacitance. The sense amplifiers are then enabled during a period of time 32, restoring the data on the bitlines and memory cells to full logic levels of the signal on the wordline, as shown at 26A, 26B, 26C and 26D. The column address of memory cell 1 (of N columns) is then enabled during an interval 27, and bitlines 26A and 26B reverse logic levels during the address interval, due to the opposite polarity of the write data, while the remaining bitlines 30 do not since the corresponding access devices are not enabled. The adddress interval then ends, followed by the sense (restore) interval 32, followed by the precharge interval.
The read sequence is identical to the write sequence up until the bitline sense amplifiers are enabled. Then the column decoder enables databus access devices 6 to transfer read data to the databus, which is then sensed by the read RMA sense amplifier.
The above sequence takes a considerable amount of time, due to the requirement to do sequential addressing.